CYRF6936
Document #: 38-16015 Rev. *F Page 29 of 39
Register Files
Files are written to or read from using non-incrementing burst read or write transactions. In most cases accessing a file may be
destructive; the file must be completely read/written, otherwise the contents may be altered. When accessing file registers, the
bytes are presented to the bus least significant byte first.
Mnemonic TX_BUFFER_ADR Address 0x20
Length 16 Bytes R/W W
Default 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in
TX_LENGTH_ADR will have no effect, and these bytes will be lost. The FIFO accumulates data until it is reset via TX CLR in TX_CTRL_ADR.
A previously sent packet, of 16 bytes or less, can be transmitted if TX_GO is set without resetting the FIFO. The contents of TX_BUFFER_ADR
is not affected by the transmission of an Auto ACK.
Mnemonic RX_BUFFER_ADR Address 0x21
Length 16 Bytes R/W R
Default 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file
register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are
handled correctly.
When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer
is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly
received packet while this file register is being read.
When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate—the first byte read is data, the second byte is a valid flag
for each bit in the first byte, the third byte is data, the fourth byte valid flags, etc. In SDR and DDR modes the valid flag for a bit is set if the
correlation coefficient for the bit exceeded the correlator threshold, and is cleared if it did not. In 8DR mode, the MSB of a valid flags byte
indicates whether or not the correlation coefficient of the corresponding received symbol exceeded the threshold. The seven LSBs contain the
number of erroneous chips received for the data.
Mnemonic SOP_CODE_ADR Address 0x22
Length 8 Bytes R/W R/W
Default
0x17FF9E213690C782
When using 32 chip SOP_CODE_ADR codes, only the first four bytes of this register are used; in order to complete the file write process, these
four bytes must be followed by four bytes of “dummy” data. However, a class of codes known as “multiplicative codes” may be used; there are
64 chip codes with good auto-correlation and cross-correlation properties where the least significant 32 chips themselves have good auto-
correlation and cross-correlation properties when used as 32-chip codes. In this case the same eight-byte value may be loaded into this file
and used for both 32 chip and 64 chip SOP symbols.
When reading this file, all eight bytes must be read; if fewer than eight bytes are read from the file, the contents of the file will have been rotated
by the number of bytes read. This applies to writes, as well.
Recommended SOP Codes:
0x91CCF8E291CC373C
0x0FA239AD0FA1C59B
0x2AB18FD22AB064EF
0x507C26DD507CCD66
0x44F616AD44F6E15C
0x46AE31B646AECC5A
0x3CDC829E3CDC78A1
0x7418656F74198EB9
0x49C1DF6249C0B1DF
0x72141A7F7214E597
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