CYRF6936
Document #: 38-16015 Rev. *F Page 30 of 39
Mnemonic DATA_CODE_ADR Address 0x23
Length 16 Bytes R/W R/W
Default
0x02F9939702FA5CE3012BF1DB0132BE6F
In GFSK mode, this file register is ignored.
In 64-SDR mode, only the first eight bytes are used.
In 32-DDR mode, only eight bytes are used. The format for these eight bytes: 0x00000000BBBBBBBB00000000AAAAAAAA, where “0”
represents unused locations. Example: 0x00000000B2BB092B00000000B86BC0DC; where “B86BC0DC” represents AAAAAAAA,
“00000000“ represents unused locations, “B2BB092B“ represents BBBBBBBB, and “00000000“ represents unused locations.
In 64-DDR and 8DR modes, all sixteen bytes are used.
When reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been
rotated by the number of bytes read. This applies to writes, as well.
Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation and cross-correlation properties, and it is recom-
mended that such sequences be used; the default value of this register is one such sequence. In typical applications, all devices use the same
DATA_CODE_ADR codes, and devices and systems are addressed by using different SOP_CODE_ADR codes; in such cases it may never
be necessary to change the contents of this register from the default value.
Typical applications should use the default code.
Mnemonic PREAMBLE_ADR Address 0x24
Length 3 Bytes R/W R/W
Default 0x333302
1st byte – The number of repetitions of the preamble sequence that are to be transmitted. The preamble may be disabled by writing 0x00 to
this byte.
2nd byte – Least significant eight chips of the preamble sequence
3rd byte – Most significant eight chips of the preamble sequence
If using 64-SDR to communicate with CYWUSB69xx devices, set number of repetitions to four for optimum performance
When reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the file will have been rotated
by the number of bytes read. This applies to writes, as well.
Mnemonic MFG_ID_ADR Address 0x25
Length 6 Bytes R R
Default NA
To minimize ~190µA of current consumption (default), execute a “dummy” single-byte SPI write to this address with a zero data stage after the
contents have been read. Non-zero to enable reading of fuses. Zero to disable reading fuses.
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