
CYRF6936
Document #: 38-16015 Rev. *F Page 4 of 39
Figure 6-2. Example ACK Packet Format
Packet Buffers
All data transmission and reception utilizes the 16-byte packet
buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16-bytes
of payload data to be loaded in one burst SPI transaction, and
then transmitted with no further MCU intervention. Similarly,
the receive buffer allows an entire packet of payload data up
to 16 bytes to be received with no firmware intervention
required until packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes, however,
actual maximum packet length will depend on accuracy of the
clock on each end of the link and the data mode; interrupts are
provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16-bytes initially, and add further
bytes to the transmit buffer as transmission of data creates
space in the buffer. Similarly, when receiving packets longer
than 16 bytes, the MCU must fetch received data from the
FIFO periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for trans-
mission and reception of acknowledged data packets.
When transmitting in transaction mode, the device automati-
cally:
• starts the crystal and synthesizer
• enters transmit mode
• transmits the packet in the transmit buffer
• transitions to receive mode and waits for an ACK packet
• transitions to the transaction end state when either an ACK
packet is received, or a timeout period expires
Similarly, when receiving in transaction mode, the device
automatically:
• waits in receive mode for a valid packet to be received
• transitions to transmit mode, transmits an ACK packet
• transitions to the transaction end state (receive mode to
await the next packet, etc.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (providing packets of 16
bytes or less are used); to transmit data the MCU simply needs
to load the data packet to be transmitted, set the length, and
set the TX GO bit. Similarly, when receiving packets in trans-
action mode, firmware simply needs to retrieve the fully
received packet in response to an interrupt request indicating
reception of a packet.
Backward Compatibility
The CYRF6936 IC is fully interoperable with the main modes
of the first generation devices. The 62.5-kbps mode is
supported by selecting 32-chip DDR mode. Similarly, the
15.675-kbps mode is supported by selecting 64-chip SDR
mode.
In this way, a suitably configured CYRF6936 IC device may
transmit data to and/or receive data from a first generation
device. Disabling the SOP, length, and CRC16 fields is
required for backwards compatibility.
Data Rates
By combining the PN code lengths and data transmission
modes described above, the CYRF6936 IC supports the
following data rates:
• 1000-kbps (GFSK)
• 250-kbps (32-chip 8DR)
• 125-kbps (64-chip 8DR)
• 62.5-kbps (32-chip DDR)
• 31.25-kbps (64-chip DDR)
• 15.625-kbps (64-chip SDR)
7.0 Functional Block Overview
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
P SOP 1 SOP 2 CRC 16
Pream ble
n x 16us
1st Fram ing
Sym bol*
2nd Fram ing
Sym bol*
CRC field from
received packet.
2 Byte periods
*Note:32 or 64us
Table 7-1. Internal PA Output Power Step Table
PA Setting Typical Output Power (dBm)
7+4
60
5–5
4 –13
3 –18
2 –24
1 –30
0 –35
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